LSI IOPS ROC & Roll

Announced last December, LSI Corporation is now shipping a 6Gb/s SAS RAID-on-Chip (ROC) (redundant array of independent disks) IC (integrated circuit) that more than doubles the RAID 5 random input/output operations per second (IOPS) to tier-one server OEMs. Intended to optimize the use of solid-state drives (SSDs) in servers, the LSI SAS2208 dual-core SAS ROC is also designed for migration to PCI Express 3.0-based servers expected to start shipping in 2012.

September 20, 2010

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Announced last December, LSI Corporation is now shipping a 6Gb/s SAS RAID-on-Chip (ROC) (redundant array of independent disks) IC (integrated circuit) that more than doubles the RAID 5 random input/output operations per second (IOPS) to tier-one server OEMs. Intended to optimize the use of solid-state drives (SSDs) in servers, the LSI SAS2208 dual-core SAS ROC is also designed for migration to PCI Express 3.0-based servers expected to start shipping in 2012.

According to Gartner's Sergis Mushell, Principal Research Analyst, the announcement is just the expected next-step after LSI started sampling the chip at the start of the year. The company already dominates the 3 and 6Gbps SAS ROC (RAID-on-Chip) market and was the largest vendor in the host bus RAID controller vendor market, but he believes the market--server OEMs and customers--are eager for the jump in IOPS performance.

"The timing is right for this technology," he says.  "A lot of environments (especially virtualized shops) are running out of IOPS, and a lot of organizations are looking at SAS ROC for reliability purposes." Moving the RAID workload from the CPU to a dedicated processor makes a lot of sense.

LSI says customers will get the best of both worlds: improved performance today and compatibility for tomorrow. It expects the biggest impact short term to be supporting the use of SSDs in tier O storage or cache where performance is critical.

The eight-port LSI SAS2208 ROC delivers up to 400,000 random IOPS in RAID 5, 6 and 10 configurations. It integrates a dual-core 800 MHz PowerPC processor and LSI MegaRAID technology that is further enhanced by combining a 72-bit DDR3-1333 SDRAM interface and specialized hardware acceleration engines with an architecture featuring multiple 500MHz, 128-bit point-to-point internal data paths.

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