The Next Step For Flash: 3D

It’s hard to overstate the impact that affordable flash memory has had in the storage business. Not since the introduction of Fibre Channel SANs in the late 90s has a new technology so significantly changed the way we use and manage storage. Today, primary storage uses flash with disk drives relegated to a secondary role holding less active data.

The problem is that we know the 2D NAND flash we’re using now has a limited future. Flash is a stored charge device, and as geometries shrink, the number of trapped electrons that indicates a given memory state in a cell also shrinks. Having fewer electrons between the 01 state and the 10 state in a Multi-Level Cell (MLC) means that the escape of just a few makes the data unreliable. Since the insulating layers also have to be thinner, they start leaking sooner as they’re eroded by the erase voltage.

We can see that effect if we look at how MLC flash endurance has fallen with each new shrink of the technology. The old Intel X25-M SSD used 50nm flash with an endurance of over 10,000 P/E cycles; today’s 1X (16-19NM) is down to about 7,000. Luckily, the ECC and signal processing capabilities of our SSD controllers have advanced faster than the flash they get to control has degraded, but at some point even smart software will meet its match.

The general consensus is that somewhere around 8nm, we reach the point where the data’s just not good enough for long enough to make it worthwhile. At that point, the overprovisioning and additional ECC the flash needs cost more than the smaller geometry saves.

Since we should be seeing 10nm flash by the end of this decade, academics and chip makers have been looking for what comes next. Samsung made it clear this week that the next step is 3D flash by announcing that it's mass producing its 3D vertical NAND (V-NAND) flash memory chip.

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Most traditional memory chips look like my new hometown of Santa Fe, N.M., where I can count the number of buildings over four stories high. They build up the floating gates that make each memory cell by stacking layers, but the cells themselves each sit on the substrate in a two-dimension array.

Samsung’s new 128Gbit chip uses a new charge-trap architecture rather than floating gate cells and stacks one charge trap on top of the other like New York stacks apartments, which increases the amount of memory Samsung can wring out of a wafer. Higher density means lower costs, which is why we shrink geometries anyway, so the 3D model should mean we can expect flash prices to continue to fall over time especially if, as it claims, Samsung can stack 24 layers.

Samsung didn’t announce how much data a cell in this new V-NAND holds or the geometry; since it achieves similar density in its 1Xnm TLC chips, I’m assuming this chip is based on an older, larger geometry.

I for one am breathing a little easier, as 3D flash should be able to fill the gap until some of the really interesting alternatives like resistive RAM (ReRAM), phase change memory (PCM) and electron spin-transfer torque memory reach maturity.