Agilent Drives Out SAN Errors

Agilent Technologies Inc. (NYSE: A) today launched its latest Fibre Channel controller chip, which embeds standard error-correction technology into silicon -- an industry first, according to the company (see Agilent Delivers FC Chips).

The company says its HPFC-5600 Tachyon DX2+ [ed. note: well that just rolls off the tongue] Fibre Channel controller is the first in the industry to include error detection code (EDC), which detects data corruption in storage subsystems.

"We're solving the problem of data integrity in hardware, so it's much faster than alternative approaches," says Erik Ottem, marketing director for Agilent's storage networking division.

EDC, which Agilent helped develop, is a double-bit error correction algorithm, meaning that it's much faster than single-bit algorithms. Moreover, unlike current error-correction techniques -- including those used in its own previous generations of the Tachyon chip -- Agilent says EDC is optimized to run in hardware and that it's well integrated at the system level with other components in a storage subsystem.

The HPFC-5600 uses EDC to flag the data error and alert the memory subsystem's software driver. That driver can then take corrective measures to recover the I/O, Agilent says. The chip's EDC algorithm maintains the SCSI command structure and architecture model, and enables EDC to stay with the data for its entire life within the storage array.However, EDC isn't an industry standard yet -- the EDC algorithm will work only with Agilent's own chips, for now. Agilent says it expects EDC to become a standard through the InterNational Committee for Information Technology Standards (INCITS) T10 committee, which oversees SCSI specifications. A vote by the T10 committee on whether to approve EDC as a standard is scheduled for November.

Ottem says EDC becomes even more important as Fibre Channel speeds increase to 4 and 10 Gbit/s in the coming years . The overhead attributable to EDC is only 1 percent, Agilent says -- far less than with systems that implement error correction in higher-layer software.

The HPFC-5600 chip supports both 1- and 2-Gbit/s Fibre Channel operation, and is backward-compatible with previous generations of Agilent's Tachyon controllers. The HPFC-5600 interfaces to either PCI or PCI-X buses, and supports both 32- and 64-bit formats. It's available now in samples; Agilent expects volume production to start in the first quarter of 2004, which is when it plans to announce pricing.

Agilent will pitch the new FC chip to enterprise storage array companies. Agilent's storage customers include EMC Corp. (NYSE: EMC), Hewlett-Packard Co. (NYSE: HPQ), Hitachi Ltd. (NYSE: HIT; Paris: PHA), IBM Corp. (NYSE: IBM), and LSI Logic Storage Systems Inc.

Also today, Agilent announced the HDMP-0528, an eight-port port bypass circuit (PBC) device for serial Fibre Channel Arbitrated Loop (FC-AL) signals within storage subsystems. One of the basic functions of the PBC is to let individual disk drives be added or removed from an array without affecting the operation of the rest of the system.Todd Spangler, US Editor, Byte and Switch